Determination of parasitic capacitance between the gate and drain/source local interconnect of a field effect transistor
US6169302A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1999 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Jul 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention accurately determines a first parasitic capacitance component between a conductive gate region to a drain local interconnect of a real field effect transistor, and determines a second parasitic capacitance component between the conductive gate region to a source local interconnect of the real field effect transistor. A virtual field effect transistor is fabricated on a dielectric in order to determine the parasitic capacitance component between just the gate and the drain or source local interconnect of the real field effect transistor. The virtual field effect transistor includes a virtual drain local interconnect, a virtual source local interconnect, and a virtual conductive gate region fabricated on the dielectric with a respective size and positions relative to each other that are substantially the same as that of the drain and source local interconnects and the gate, respectively, of the real field effect transistor. In this manner, the first parasitic capacitance component between the conductive gate region of the real field effect transistor to the drain local interconnect of the real field effect transistor is a first capacitance measured between the v…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.