Chamber liner for semiconductor process chambers
US6170429A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1998 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Sep 30, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S156/916
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A chamber liner for use in a semiconductor process chamber and a semiconductor process chamber containing the chamber liner are disclosed. The process chamber includes a housing having an inner surface defining a chamber in which a vacuum is drawn during processing of a semiconductor wafer. The chamber liner has a plasma confinement shield with a plurality of apertures. An outer sidewall extends upwardly from the plasma confinement shield. An outer flange extends outwardly from the outer sidewall such that the outer flange extends beyond the chamber and into a space at atmospheric pressure. The chamber liner preferably further includes an inner sidewall that extends upwardly from the plasma confinement shield. The plasma confinement shield, the inner and outer sidewalls, and the outer flange are preferably integral with one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.