Method for bringing up lower level metal nodes of multi-layered integrated circuits for signal acquisition
US6171944A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 1998 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | May 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for bringing up lower level metal nodes of multi-layered IC devices (200) includes a step of boring a passage (210) down through the obstructing or non-target metal layers (220) exposing these layers, through the Inter Layer Dielectric layers (230), stopping at the target metal layer (240), and a step of depositing Gallium implanted insulator (250, 260) forming a node structure (280) with a conductive core (250) and an insulative sheath (260). The conductive core (250) brings up the target metal node or layer (240) and the insulative sheath (260) isolates the exposed non-target metal nodes or layers (220) from the target metal node (240) and the conductive core (250).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.