Low-noise vertical bipolar transistor and corresponding fabrication process
US6177717A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Jun 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/138
Abstract
The intrinsic collector of a vertical bipolar transitor is grown epitaxially on an extrinsic collector layer buried in a semiconductor substrate. A lateral isolation region surrounds the upper part of the intrinsic collector and an offset extrinsic collector well is produced. An SiGe heterojunction base lying above the intrinsic collector and above the lateral isolation region is produced by non-selective epitaxy. An in-situ doped emitter is produced by epitaxy on a predetermined window in the surface of the base which lies above the intrinsic collector so as to obtain, at least above the window, an emitter region formed from single-crystal silicon and directly in contact with the silicon of the base.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.