Multi-stage method for forming optimized semiconductor seed layers
US6187670A · kind A · utility
23Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1998 |
| Grant date | Feb 13, 2001 |
| Priority date | — |
| Expiry date | Dec 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1089
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming seed layers in semiconductor channel and via openings by using a two-stage approach after lining the channel and via openings with barrier material. First, a low temperature deposition of a seed layer is performed at below the 250.degree. C. at which conductive material agglomeration occurs. Second, a higher temperature deposition of a seed layer is performed at above 250.degree. C. Then, the conductive material is deposited to fill the channel and via openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.