Method for plating gold to bond leads on a semiconductor substrate
US6190529A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1999 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Apr 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for plating gold to a plurality of bond leads on a substrate is disclosed. The method first extends a plating line from a plating loop on the edge of the substrate to a bond area in the center portion of the substrate to electrically connect the plurality of bond leads in series. The plating line further extends to connect to the plating loop after connecting the plurality of bond leads together. Then, electricity is applied to the plurality of bond leads via the plating loop and the plating line thereby plates gold to the plurality of bond leads. Finally, a bonding tool is used to cut off and remove the plating line when the bonding tool is provided to bond the plurality of bond leads to a die that is attached to the substrate, whereby the residual plating line remaining on the substrate does not affect the performance of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.