Method for forming graded LDD transistor using controlled polysilicon gate profile
US6191044A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1998 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Oct 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having reduced polysilicon gate length, reduced parasitic capacitance and gradual doping profiles is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a polysilicon gate, wherein the polysilicon gate comprises sidewalls with re-entrant profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles. The gradual doping profiles reduce parasitic capacitance and minimize hot carrier injections. Portions of the polysilicon gates with re-entrant profiles are used as mask during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of the bottom portion of the polysilicon gates. Since the LDD structures are spaced away from the edges of the polysilicon gates, the lateral diffusion of th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.