Three-dimensional power modeling table having dual output capacitance indices
US6195630A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1999 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | May 10, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99942
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.