System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom
US6202101A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1998 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Sep 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue. Thus, the in-order queue keeps track of the order in which data is transferred …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.