Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects
US6204138A · kind A · utility
37Cited by
12References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1999 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Mar 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6715
Abstract
A method of forming a MOSFET device is provided. First lightly doped regions are formed, the first lightly doped regions including LDD extension regions of the device. Second very lightly doped regions are formed at least partially below the first lightly doped regions, respectively, the second very lightly doped regions having a dopant concentration less than the first lightly doped regions, and the second very lightly doped regions being implanted at a higher energy level than the first lightly doped regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.