Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAG
US6205560A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1996 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Feb 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for diagnosing and debugging a processor for executing a stream of instructions that includes a set of debug registers for identifying an instruction or data address breakpoint; a processor for generating a debug exception in response to an instruction or data address in the stream of instructions matching the instruction or data breakpoint stored in the set of debug registers and a debug configuration register for enabling transfer of program control to one of a plurality of destinations in response to the debug exception. The debug configuration registers may designate system management mode, JTAG routine or a software debug interrupt handler as the destination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.