Metallization technique for gate electrodes and local interconnects
US6207543A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a trench exposing a contact region for each transistor. This trench is filled with a metal, such as tungsten to provide an electrical interconnection of the contact regions. The metal is then planarized to be approximately coplanar with the planarized oxide layer. Metal gate electrodes are formed at the same time as the interconnection. Additional processing includes depositing an IMO layer over the planarized metal and oxide and defining additional interconnections through the IMO layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.