Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide etch stop layer
US6207576A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Jan 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02118
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A trench is etched into the second low k dielectric layer, followed by the etching of a via into the first low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the first low k dielectric material and not the second low k dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.