Inventor · Milpitas, CA, US

Jerry Cheng

28Patents
10h-index
33Co-inventors
75Inventor score

Filing activity: Jun 4, 1998 → May 7, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US6235628A Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer Electricity 35 Expired
US6472317B1 Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers Electricity 24 Expired
US6153514A Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer Electricity 20 Expired
US6291887A Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer Electricity 20 Expired
US6086777A Tantalum barrier metal removal by using CF.sub.4 /o.sub.2 plasma dry etch Electricity 17 Expired
US8060510B2 Best fit map searching Emerging Cross-Sectional Technologies 15 Active
US6207577A Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer Electricity 15 Expired
US6207576A Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide etch stop layer Electricity 12 Expired
USD434595S Electric ice-scraping machine General 11 Expired
US6255735A Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers Electricity 10 Expired
US10942625B1 Coordinated display of software application interfaces Physics 8 Active
US8862610B2 Method and system for content search Physics 7 Active
US6107208A Nitride etch using N.sub.2 /Ar/CHF.sub.3 chemistry Electricity 7 Expired
US6380091B1 Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer Electricity 5 Expired
US6649525B1 Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process Electricity 3 Expired
US11025742B2 Dynamic link processing engine Electricity 3 Active
US6756300B1 Method for forming dual damascene interconnect structure Electricity 2 Expired
US10719600B1 Application authenticity verification in digital distribution systems Electricity 2 Active
US6759179B1 Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process Electricity 1 Expired
US11768930B2 Application authenticity verification in digital distribution systems Electricity 1 Active
US11003757B1 Application authenticity verification in digital distribution systems Electricity 0 Active
US10977060B2 Native execution bridge for sandboxed scripting languages Physics 0 Active
US11729295B2 Dynamic link processing engine Electricity 0 Active
US11231921B2 Software application update management engine Physics 0 Active
US10394584B2 Native execution bridge for sandboxed scripting languages Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.