Method for manufacturing PMOS transistor
US6211027A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 19, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Nov 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a PMOS transistor. A gate terminal is formed over a substrate. Spacers are formed on the sidewalls of the gate terminal. A source/drain terminal is formed in the substrate on each side of the gate terminal, and then a metal silicide layer is formed over the top surface of the gate terminal and the substrate. The spacers are next removed. Using the metal silicide layer as a mask, a source/drain extension region is formed in the substrate between the gate terminal and the source/drain terminal. Similarly, using the metal silicide layer as a mask, an anti-punchthrough region is form in the substrate interior under the source/drain extension region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.