Method of fabricating flux concentrating layer for use with magnetoresistive random access memories

US6211090A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Mark Durlam · Chandler, US
• Eugene Chen · Gilbert, US
• Saied N. Tehrani · Tempe, US
• Jon Slaughter · Tempe, US
• Gloria Kerszykowski · Fountain Hills, US
• Kelly Kyler · Mesa, US

Key dates

• Filing date: Mar 21, 2000
• Grant date: Apr 3, 2001
• Expiry date: Mar 21, 2020

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B82Y10/00
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A method of fabricating a flux concentrator for use in magnetic memory devices including the steps of providing at least one magnetic memory bit (10) and forming proximate thereto a material stack defining a copper (Cu) damascene bit line (56) including a flux concentrating layer (52). The method includes the steps of depositing a bottom dielectric layer (32), an optional etch stop (34) layer, and a top dielectric layer (36) proximate the magnetic memory bit (10). A trench (38) is etched in the top dielectric layer (36) and the bottom dielectric layer (32). A first barrier layer (42) is deposited in the trench (38). Next, a metal system (29) is deposited on a surface of the first barrier layer (42). The metal system (29) includes a copper (Cu) seed material (44), and a plated copper (Cu) material (46), a first outside barrier layer (50), a flux concentrating layer (52), and a second outside barrier layer (54). The metal system (29) is patterned and etched to define a copper (Cu) damascene bit line (56).