Method and apparatus for minimizing parasitic resistance of semiconductor devices
US6218250A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1999 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Jun 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a gate structure, a plurality of sidewall spacers, and a plurality of first silicide layers. The gate structure is positioned above the substrate. The plurality of sidewall spacers are positioned adjacent to the gate structure. The first silicide layers are positioned in the substrate and have first ends that extend underneath the sidewall spacers. A method for forming a semiconductor device includes forming a gate structure above a substrate. A plurality of sidewall spacers are formed adjacent the gate structure. An implant material is disposed into the substrate using a tilted implantation process that is adapted to form first implant regions in the substrate. The implant regions have first ends that extend underneath the sidewall spacers by a first distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.