Method of fabricating an integrated circuit having punch-through suppression
US6221724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1998 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Nov 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2658
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and method of fabrication is provided for an integrated circuit having punch-through suppression. Unlike conventional methods of punch-through suppression wherein a dopant implant is fabricated in the device, the present invention utilizes an inert ion implantation process whereby inert ions are implanted through a fabricated gate structure on the semiconductor substrate to form a region of inert ion implant between source and drain regions of a device on the integrated circuit. This accumulation region prevents punch-through between source and drain regions of the device. In a second embodiment, the inert ion implantation is used in conjunction with the conventional punch-through dopant implant. In this second embodiment, diffusion of the implant during subsequent thermal annealing is suppressed by the inert ion accumulation in the subsurface region of the device. Accordingly, improved integrated circuits and methods of fabricating an integrated circuit having punch-through suppression are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.