Method of constructing stacked packages
US6222265A · kind A · utility
117Cited by
34References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Dec 17, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprising multiple stacked substrates having flip chips attached to the substrates with chip-on-board assembly techniques to achieve dense packaging. The substrates are preferably stacked atop one another by electric connections which are column-like structures. The electric connections achieve electric communication between the stacked substrates, must be of sufficient height to give clearance for the components mounted on the substrates, and should preferably be sufficiently strong enough to give support between the stacked substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.