Method for minimizing program disturb in a memory cell
US6222761A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2000 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Jul 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of applying voltages to a memory cell, such as a P-channel EEPROM cell, and in particular to applying voltages to the cell during an erase operation of the cell is described. The method recognizes that during an erase, memory cells sharing deselected word lines are susceptible to a type of program disturb which is subtle and gradually causes corruption and loss of data over many programming cycles. The method of the present invention applies a voltage to deselected word lines, which is lower in magnitude than a programming voltage. This reduces the rate at which program disturb occurs, markedly increasing the number of programming cycles to which the deselected cells may be subjected before becoming susceptible to loss of data. The endurance of the memory array is thus significantly extended.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.