Kent Hewitt
18Patents
7h-index
22Co-inventors
66Inventor score
Filing activity: Apr 1, 1993 → Aug 13, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5488711A | Serial EEPROM device and associated method for reducing data load time using a page mode write cache | Physics | 92 | Expired |
| US5363334A | Write protection security for memory device | Physics | 49 | Expired |
| US5367484A | Programmable high endurance block for EEPROM device | Physics | 33 | Expired |
| US5675622A | Method and apparatus for electronic encoding and decoding | Physics | 25 | Expired |
| US6222761A | Method for minimizing program disturb in a memory cell | Physics | 12 | Expired |
| US5764099A | Integrated voltage regulating circuit useful in high voltage electronic encoders | Electricity | 10 | Expired |
| US5675534A | Method and apparatus for preventing unauthorized access to nonvolatile memory in electronic encoders having a voltage level detection circuit | Physics | 7 | Expired |
| US6236595A | Programming method for a memory cell | Physics | 7 | Expired |
| US5604701A | Initializing a read pipeline of a non-volatile sequential memory device | Physics | 6 | Expired |
| US6150864A | Time delay circuit which is voltage independent | Electricity | 5 | Expired |
| US6300183A | Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor | Electricity | 5 | Expired |
| US6504191B2 | Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor | Electricity | 4 | Expired |
| US7466591B2 | Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits | Electricity | 3 | Active |
| US7817474B2 | Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits | Electricity | 2 | Active |
| US9455037B2 | EEPROM memory cell with low voltage read path and high voltage erase/write path | Electricity | 2 | Active |
| US8094503B2 | Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits | Electricity | 1 | Active |
| US10910058B2 | Shared source line memory architecture for flash cell byte-alterable high endurance data memory | Physics | 1 | Active |
| US9343147B2 | Resistive random access memory (ReRAM) and conductive bridging random access memory (CBRAM) cross coupled fuse and read method and system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.