Wafer-level package and methods of fabricating
US6228687A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantially through the length thereof. The carrier may also include laterally extending conductive traces in contact with or otherwise in electrical communication with the conductive material in the apertures of the carrier. Contacts may be disposed on a backside surface of the carrier. The contacts may communicate with the conductive material disposed in the apertures of the carrier. A conductive bump, such as a solder bump, may be disposed adjacent each or any of the contacts. A chip-scale package including the carrier of the present invention is also within the scope of the present invention. Such a chip-scale package includes a semiconductor device invertedly disposed over the carrier such that bond pads of the semiconductor device substantially align with apertures formed through the carrier. Thus, the bond pads of the semiconductor device may communicate with the conductive bumps by means of the conductive material dispose…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.