Store instruction having vertical memory hierarchy control bits
US6230242A · kind A · utility
0Cited by
9References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Aug 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A STORE instruction having vertical memory hierarchy control bits is disclosed. The STORE instruction comprises an operation code field, a write-through field, and a vertical write-through level field. The vertical write-through level field indicates a vertical memory level within a memory hierarchy to which the STORE operation should be applied, when the write-through field is set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.