Wafer level burn-in of memory integrated circuits
US6233185A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Feb 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.