Method for fabricating stackable chip scale semiconductor package
US6235554A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1999 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | May 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package. The method for fabricating the package includes the steps of: laser machining and etching the vias, forming an insulating layer in the vias, and then depositing a conductive material within the vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.