Programming method for a memory cell
US6236595A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2000 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Jul 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.