Method for improving electrostatic discharge (ESD) robustness
US6238975A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1998 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Nov 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
In a non-volatile memory comprising a region 2 for core memory cells and a peripheral region 4a on a substrate 6, a method for improving electrostatic discharge (ESD) robustness of the non-volatile memory comprises the steps of lightly doping the source and drain regions 18 and 20 of a peripheral transistor 12 in the peripheral region 4a with a first n-type dopant, providing a double diffusion implant mask 10 having an opening over the region 2 for the core memory cells and also an opening 8 over the peripheral region 4a, and performing a double diffusion implantation through the opening 8 over the peripheral region 4a. In an embodiment, the step of performing the double-diffusion implantation comprises the steps of implanting a second n-type dopant comprising phosphorus into the source and drain regions 18 and 20, and implanting a third n-type dopant comprising arsenic into the source and drain regions 18 and 20 subsequent to the step of implanting the second n-type dopant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.