Low resistance power MOSFET or other device containing silicon-germanium layer

US6239463A · kind A · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Richard K. Williams · Cupertino, US
• Mohamed N. Darwish · Campbell, US
• Wayne B. Grabowski · Los Altos, US
• Michael E. Cornell · Campbell, US

Key dates

• Filing date: Aug 28, 1997
• Grant date: May 29, 2001
• Expiry date: Aug 28, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/156

Abstract

A power MOSFET or other semiconductor device contains a layer of silicon combined with germanium to reduce the on-resistance of the device. The proportion of germanium in the layer is typically in the range of 1-40%. To achieve desired characteristics the concentration of germanium in the Si-Ge layer can be uniform, stepped or graded. In many embodiments it is desirable to keep the germanium below the surface of the semiconductor material to prevent germanium atoms from being incorporated into a gate oxide layer. This technique can be used in vertical DMOS and trench-gated MOSFETs, quasi-vertical MOSFETs and lateral MOSFETs, as well as insulated gate bipolar transistors, thyristors, Schottky diodes and conventional bipolar transistors.