Device improvement by lowering LDD resistance with new silicide process

US6242776A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Frederick N. Hause · Austin, US
• Manfred Horstmann · Dresden, DE
• Karsten Wieczorek · Dresden, DE

Key dates

• Filing date: Jun 2, 1999
• Grant date: Jun 5, 2001
• Expiry date: Jun 2, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227

Abstract

A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and removing a first portion of the dielectric layer above the gate conductor and above the LDD region. The method also includes forming a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD region and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.