Method of forming via
US6245667A · kind A · utility
3Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1999 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Dec 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a via. A stacked structure has a barrier layer and a metal line is formed over a substrate. Spacers capable of serving as a barrier are formed over tapering sidewalls of the stacked structure before vias and plugs are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.