Symmetrical program and erase scheme to improve erase time degradation in NAND devices
US6246610A · kind A · utility
30Cited by
24References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2000 |
| Grant date | Jun 12, 2001 |
| Priority date | — |
| Expiry date | Feb 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programming and erase method that extends erase time degradation of nonvolatile memory devices by using a constant erase voltage and a set of program voltages, where the average program voltage of the set of the program voltages is approximately equal to the constant erase voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.