Semiconductor device having patterned metal layer over a polysilicon line and method of fabrication thereof
US6249032A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Oct 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and fabrication process are provided in which a patterned metal layer is formed over a polysilicon line. The polysilicon line is disposed on a substrate and may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and the patterned metal layer is formed over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the patterned metal layer may extend over the top of the second polysilicon line and interconnect the two polysilicon lines. A contact for the polysilicon line is coupled to the patterned metal layer. The use of a patterned metal line may provide a larger footprint for the contact then the underlying polysilicon line(s) and may decrease the sheet resistance to the polysilicon line(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.