Store instruction having horizontal memory hierarchy control bits
US6249843A · kind A · utility
3Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1999 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Aug 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A STORE instruction having horizontal memory hierarchy control bits is disclosed. The STORE instruction comprises an operation code field, a write-through field, and a horizontal write-through level field. The horizontal write-through level field indicates a horizontal memory level within a multi-level memory hierarchy to which the STORE operation should be applied, when the write-through field is set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.