Optimizing compiler for generating store instructions having memory hierarchy control bits
US6249911A · kind A · utility
4Cited by
9References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1999 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Aug 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An optimizing compiler for generating STORE instructions having memory hierarchy control bits is disclosed. The compiler first converts a first STORE instruction to a second STORE instruction. The compiler then provides an operation code field within the second instruction for indicating an updating operation. The compiler further provides a vertical write-through level field within the second instruction for indicating a vertical memory level and a horizontal memory level within a multi-level memory hierarchy to which the updating operation should be applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.