Apparatus for adjusting a store instruction having memory hierarchy control bits
US6253286A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1999 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Aug 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for adjusting a STORE instruction having memory hierarchy control bits is disclosed. A multiprocessor data processing system includes a multi-level memory hierarchy. The apparatus for adjusting control bits within an instruction to be utilized within the multi-level memory hierarchy comprises a performance monitor and a bit adjuster. The memory hierarchy control bits indicates a memory level within the multi-level memory hierarchy to which an updating operation should be applied. In response to the outputs from the performance monitor, the bit adjuster alters at least one of the memory hierarchy control bits within the instruction in order to achieve optimal performance for the updating operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.