Method for fabricating high-performance submicron MOSFET with lateral asymmetric channel
US6255219A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1999 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Sep 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
The present invention provides a method for fabricating a submicron metal-oxide semiconductor field-effect transistor (MOSFET). The method includes providing a gate on a substrate, the substrate having a source side and a drain side, the drain side having a spacer area; forming a spacer at the spacer area; and performing a halo implant at the source side and the drain side, wherein the spacer prevents implantation in the spacer area, wherein the spacer facilitates formation of a lateral asymmetric channel. In the preferred embodiment, the spacer is formed by depositing an oxide layer on the gate and substrate, and then avoiding nitrogen implantation of the oxide layer in the spacer area while implanting nitrogen in the remainder of the oxide layer. The difference in the etch rates of oxide implanted with nitrogen and oxide not implanted with nitrogen allows for a selective etch of the oxide layer, resulting in the spacer in the spacer area. A lateral asymmetric channel is thus formed, and the speed of the submicron MOSFET is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.