Semiconductor device having a lead portion with outer connecting terminals
US6255740A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1997 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | May 1, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion. Also, the semiconductor device has a semiconductor chip having a predetermined number of electrode pads, a predetermined number of leads electrically connected to the electrode pads, each of the leads having a projecting terminal portion formed by bending the lead, and a resin portion sealing the semiconductor chip and the leads, wherein the terminal portions are exposed from one fa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.