Patent · US Expired

Test circuit for testing a digital semiconductor circuit configuration

US6256243A · kind A · utility

8Cited by

1References

21Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Dominique Savignac · Ismaning, DE
Wolfgang Nikutta · Birkenfeld, DE
Michael Kund · Bad Aibling, DE
Jan Ten Broke · Zwolle, NL

Key dates

Filing date	Aug 17, 2000
Grant date	Jul 3, 2001
Priority date	—
Expiry date	Aug 17, 2020

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/38
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A monolithically integrated test circuit for testing a digital semiconductor circuit configuration that is formed on the same semiconductor chip and has a large number of elements to be tested. The test circuit has a test data pattern register for temporary storage of a test data pattern, a read and write circuit for writing and reading the data in the test data pattern register to and from the elements to be tested, and a comparison circuit. The comparison circuit tests for any difference between the data written to and read from the elements to be tested. The test circuit has a pattern variation circuit, which can be activated by an activation signal and varies the test data pattern from the test data pattern register before writing into the elements to be tested.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.