Method of making stacked chip package
US6258626A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2000 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Jul 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a stacked chip package comprises the steps of: (a) placing a first chip onto a substrate in a manner that solder bumps on the first chip are aligned with corresponding flip-chip pads formed on a surface of the substrate; (b) reflowing the solder bumps; (c) attaching a second chip to the first chip through an adhesive layer; (d) curing the adhesive layer; (e) forming an underfill between the first chip and the substrate; (f) curing the underfill; (g) electrically coupling the second chip to corresponding wire-bondable pads formed on the surface of the substrate; and (h) encapsulating the first chip and the second chip against a portion of the surface of the substrate. This invention is characterized in that the adhesive layer is cured before underfilling thereby forming a protection layer on the first chip. Therefore, the cured adhesive layer can help the first chip to resist stresses created during curing process of the underfill, thereby reducing the problem of die cracking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.