Method for forming semiconductor seed layers by high bias deposition
US6261946A · kind A · utility
27Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1999 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Jan 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming seed layers in a channel or via by applying a high bias to the material of the seed layer during deposition. This sputters off the seed layer overhang in order to reduce the electrical resistance of the seed layer, maintain its barrier effectiveness and enhance the subsequent filling of the channel or via by conductive materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.