Dual gate oxide process for uniform oxide thickness

US6261972A · kind A · utility

Assignees

• Infineon Technologies AG · DE
• International Business Machines Corporation · US

Inventors

• Helmut Tews · Poughkeepsie, US
• Mary E. Weybright · Pleasant Valley, US
• Stephan Kudelka · Radeberg, DE
• Oleg Gluschenkov · Poughkeepsie, US
• Suri Hegde · New York, US

Key dates

• Filing date: Nov 6, 2000
• Grant date: Jul 17, 2001
• Expiry date: Nov 6, 2020

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/981
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising: PA1 a) growing a sacrificial oxide layer on a substrate; PA1 b) implanting a dopant through the sacrificial oxide layer; PA1 c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; PA1 d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface; PA1 e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide; PA1 f) implanting a second dosage of nitrogen ions through the photoresist; PA1 g) stripping the photoresist and the sacrificial oxide layers; and PA1 h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.