Memory cell having trench capacitor and vertical, dual-gated transistor

US6262448A · kind A · utility

Assignee

• Infineon Technologies North America Corp. · US

Inventors

• Gerhard Enders · Glen Allen, US
• Matthias Ilg · Fishkill, US
• Lothar Risch · Neubiberg, DE
• Dietrich Widmann · Unterhaching, DE

Key dates

• Filing date: Apr 30, 1999
• Grant date: Jul 17, 2001
• Expiry date: Apr 30, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/395

Abstract

A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell. With such an arrangement a DRAM cell is provided having a relatively occupies a relatively small amount of surface area of the semiconductor body.