Method to fabricate a thick oxide MOS transistor for electrostatic discharge protection in an STI process

US6265251A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Cai Jun · Singapore, SG
• Keng Foo Lo · Singapore, SG

Key dates

• Filing date: May 8, 2000
• Grant date: Jul 24, 2001
• Expiry date: May 8, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

A new method of forming a thick oxide MOS transistor for electrostatic discharge protection in a standard sub-micron STI CMOS process for an integrated circuit device has been achieved. A first well and a second well are implanted. The wells are counter-doped to the substrate type. The first well forms the drain, and the second well forms the source. A thin oxide layer is formed. A polysilicon layer is deposited. The polysilicon layer is patterned to form a dummy floating gate. Ions are implanted into the first well to form a first lightly-doped region and into the second well to form a second lightly-doped region of the same type as the wells. The lightly-doped regions are self-aligned to the dummy floating gate. Sidewall spacers are formed on the floating dummy gates. Ions are implanted into the first well to form a first heavily-doped region and the second well to to form a second heavily-doped region of the same type as the wells. The heavily-doped regions are self-aligned to the sidewall spacers. An interlevel dielectric layer is deposited. A metal layer is deposited overlying the interlevel dielectric layer. The metal layer is patterned to form the gate electrode.