High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device
US6265268A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 25, 1999 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Oct 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a top oxide layer using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800.degree. C. by either an LPCVD or RTCVD deposition processor. The process further includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the top oxide layer using an HTO deposition process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.