Circuit fabrication method which optimizes source/drain contact resistance
US6265291A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1999 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Jan 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an integrated circuit to optimize the contact resistance between impurity diffusing layers and silicide is disclosed herein. The method includes implanting a first material to a layer of semiconductor to create a buried amorphous silicon layer; implanting a second material in the layer of semiconductor and buried amorphous layer, forming a dopant profile region with a curved shape; depositing a layer of metal on the layer of semiconductor; melting the buried amorphous layer to reconfigure the curved shape to a substantially vertical profile of maximum dopant concentration; and forming silicide with the layer of semiconductor and layer of metal, the bottom of the silicide located in the vertical shape on the dopant profile region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.