Multi-chip integrated circuit package structure for central pad chip
US6265763A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2000 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Mar 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip IC package for central pad chips is proposed, which can be used to pack one peripheral-pad IC chip and at least one central-pad IC chip therein. The multi-chip IC package includes a specially-designed lead frame having a central die pad and a lead portion separated from the central die pad by a gap. The central-pad IC chip is partly attached to the lead portion of the lead frame and partly attached to the central die pad of the lead frame such that the central pads on the central-pad IC chip can be aligned with the gap of lead frame so as to allow bonding wires electrically connecting the central-pad IC chip with the lead portion of the lead frame to pass therethrough. The characterized package allows the bonding wires applied to the central-pad IC chip to be short in length so as to retain IC performance and save manufacture cost, making this multi-chip IC package structure more advantageous to use than the prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.