Method of erasing non-volatile memory cells
US6266281A · kind A · utility
132Cited by
52References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2000 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Feb 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0475
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing a memory cell that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a first voltage across the gate and the first region so that a first portion of the initial amount of charge is removed from the charge trapping region. Next, a second voltage is applied across the gate and the first region so that a second portion of the initial amount of charge is removed from the charge trapping region, wherein the second voltage is different than the first voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.