Method of forming wires on an integrated circuit chip
US6268293A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 18, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Nov 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C.sub.4 F.sub.8, 20-80 sccm of CO, 2-30 sccm of O.sub.2 and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.