Circuit and method for a multiplexed redundancy scheme in a memory device
US6269035A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2000 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Oct 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a memory-cell array divided into a plurality of memory sub-arrays that are arranged into rows and columns of memory cells. Each of the sub-arrays has a limited number of redundant rows and columns to repair defective memory cells. The redundant memory of at least two memory sub-arrays is coupled to an I/O line through a respective isolation circuit. A control circuit coupled to the isolation circuits selectively couples the redundant memory of the sub-arrays to the I/O line. Coupling the redundant memory of multiple sub-arrays facilitates using the redundant memory of one sub-array to repair the defective memory cells in other sub-arrays also coupled to the I/O line, when the redundant memory primarily associated with the other sub-arrays has been depleted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.