Integrated memory
US6272035A · kind A · utility
9Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2000 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Jul 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has an input circuit, which is provided adjacent to two groups of memory cells and via which two global data lines are connected to two local data lines. The memory has two operating states during which it feeds the data provided on the global data lines in respective different assignments to the two local data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.